The Layout Implementations of High-Speed Low-Power Sequential Logic Cells Based on MOS Current-Mode Logic

MOS Current-Mode Logic (MCML) is usually used for high-speed applications. In this paper, the design method of the high-speed low-power MCML is addressed. The layout implementations of MCML D-Flip flop cells are presented at a NCSU FreePDK 45nm technology. A mod-10 counter based on the proposed D-Flip flop cells is implemented to verify the efficiency of the proposed design method. The post-layout simulations are carried out. For normal supply voltage, the MCML sequential logic circuit can save more energy and have better performance than the traditional CMOS counterparts at 1GHz or higher operation frequencies. Scaling down the supply voltage of MCML circuits is investigated. The results show that the power consumption of MCML circuits can be reduced by lowering the supply voltage without performance degrading.